1. Field of the Invention
The present invention relates to a protection device and more particularly to a semiconductor protection circuit for protecting semiconductor integrated circuits (LSI) from damage occurring due to static electricity, etc.
2. Description of Related Art
In the related art, a protection circuit was formed in the vicinity of the LSI chip for the purpose of preventing damage to the internal components of the LSI due to static electricity applied from external sections. FIG. 6 is drawings showing an example of the protective device of the related art. FIG. 6A is a circuit diagram of the related art. FIG. 6B and FIG. 6C are flat views of the PNP bipolar transistor 120 of the related art. FIG. 6D is a cross sectional view taken-along lines A-A′ shown in FIG. 6C and FIG. 6B. The protection circuit for the I/O pad 1 as the example shown in FIG. 6A, is made up of a PNP bipolar transistor 20. The emitter (E) of the PNP bipolar transistor 20 connects to the I/O pad 1, the base (B) connects to the high voltage potential supply (VDD) 2, and the collector (C) connects to the low voltage potential supply (VSS) 3. The protection circuit for the high voltage potential supply (VDD) 2 is made up of a power supply diode 22. The anode of the power supply diode 22 connects to the high voltage potential supply (VDD) and the cathode connects to the low voltage potential supply (VSS) 3.
The PNP bipolar transistor 20 is described next. As shown in FIG. 6D, component isolation regions 12 such as a field oxidation film are selectively formed on the surface of the P-type substrate 11. An N well 13 is formed on the surface region of the P-type substrate 11. A P+ diffusion layer 14a connected with the I/O pad 1, and a P+ diffusion layer 14b connected to the low voltage potential supply (VSS) 3 are formed on one of the surface regions of the N well 13 isolated by the component isolation regions 12. An N+ diffusion layer 15 connecting to the high voltage potential supply (VDD) 2 is formed on the other surface region of the N well 13.
When-positive static electricity is applied to the I/O pad 1, in the case of this protection circuit, the snapback operation of the PNP bipolar transistor 20 causes a current to flow from the P+ diffusion layer 14a connected to the I/O pad 1, to the P+ diffusion layer 14b connected to the low voltage potential supply (VSS) 3, and this electrical current protects the internal circuit 21. When negative static electricity is applied to the I/O pad 1, the breakdown operation of the parasitic diode 23 of the PNP bipolar transistor 20 causes a current to flow from the P+ diffusion layer 14a connected to the I/O pad 1, to the N+ diffusion layer 15 connected to the high voltage potential supply (VDD) 2, and this electrical current protects the internal circuit 21. When positive static electricity is applied to the high voltage potential supply (VDD) 2, the breakdown operation of the power supply diode (power supply Di) 22, causes a current to flow to the P+ diffusion layer 14b connected to the low voltage potential supply (VSS) 3, and this electrical current protects the internal circuit 21.
FIG. 7 is a drawing showing the chip layout of the semiconductor integrated circuit (LSI: Large Scale Integrated Circuit). The protection circuit for each terminal is formed in the vicinity of that terminal. The high voltage potential supply (VDD) 2, the low voltage potential supply (VSS) 3, and the I/O pad 1 are optional and vary according to each product.
However, the technology of the related art described in JP-A NO. 120412/1994 had no room for improvement in the following points.
When the power supply pad positions were separated by a particular distance from the high voltage potential supply (VDD) and low voltage potential supply (VSS) in the semiconductor integrated circuit, the other side of the power supply wiring for the power supply protection circuit formed hear that power supply pad became extremely long. So that in some cases the power-supply wiring resistance reached a large value of several dozen ohms. Also, the circuit and layout were designed for an extremely low wiring resistance of less than 1 ohm as a countermeasure to power supply fluctuations in power supplied to the internal circuit. When positive static electricity was applied to a power supply terminal such as for the high voltage potential supply (VDD), the voltage rise across the power supply wiring resistors (R1, R2) connected to the power supply diode could not be ignored, and the current clamping ability of the power supply diode dropped drastically.
Here, since the breakdown voltage of the parasitic diode connected to the collector electrode and the breakdown voltage of the diode connected to the emitter electrode were designed to be the same figure, positive static electricity applied to a power supply terminal such as the high voltage potential supply (VDD), then flowed to the small internal circuit made up of the power supply wiring resistors. The related art therefore had the problem that internal circuits might sustain damage from low voltage static electricity and so there is still room for further improvement.
One method to eliminate the above problem, utilized the low resistance of the power supply wiring resistors (R1, R2) connected to the power supply diodes. However on a product where the high voltage potential supply (VDD) and low voltage potential supply (VSS) power supply pad positions were separated by several millimeters, a wiring resistance width of several hundred micrometers was required. This larger wiring resistance width led to a large chip size and cost increases so the related art still required further improvement. Another method to resolve the above problems, added a power supply diode however this method also led to a large chip size and cost increases and so the related art still requires further improvement.